The present invention relates to a semiconductor integrated circuit (IC), and more particularly to an IC provided with a voltage-drop or voltage lowering circuit which lowers a system supply voltage to generate an internal supply voltage.
For improving the performance of an IC, such as a memory IC, it is required to provide higher integration and lower power consumption. Especially, it is understood that lower power consumption and high-speed operation is most important.
To improve the degree of integration of an IC, transistors are fabricated to be small in size. In a conventional IC using a 5V of standard supply voltage, it is difficult to ensure the reliability of the IC, because small size of transistors have lower breakdown voltages. Especially, memory ICs of 16M bit or higher have very low breakdown voltages. It has been required to provide both lower power consumption and higher reliability by generating optimum supply voltage for each type of IC. However, it is not practically good to use different power supply circuit for each IC. Accordingly, in recent years, a voltage-drop circuit or voltage lowering circuit has been propose d and put in use. Such a voltage lowering circuit lowers a system supply voltage, supplied from an external supply circuit, to an appropriate internal supply voltage to be used for operation of t he IC.
In a conventional IC includes a voltage lowering circuit lowers a system voltage VCC (for example, 5V) to an internal supply voltage IVCC (for example 2.0V), which is lower than a breakdown voltage VB (for example, 2.5V) of a memory circuit. The internal supply voltage IVCC, generated in the voltage lowering circuit, is supplied to the memory circuit.
According to the conventional IC, different levels of system voltages VCC can be used for operating the internal circuitry. If the system voltage VCC is lower than the breakdown voltage VB of the memory circuit, the voltage lowering circuit is unnecessary to use. If the system voltage VCC of 2V, which is lower than the breakdown voltage VB of the memory circuit, is used, the voltage lowering circuit would function as impedance; and as a result, the operation speed of the IC may be undesirably decreased. To avoid such a problem, the IC must be fabricated with a conductive pattern which makes a short circuit at the voltage lowering circuit. In other words, it is required to fabricate ICs using different patterns for different system voltages.
Accordingly, an object of the present invention is to provide a semiconductor integrated circuit which operates with an appropriate supply voltage without undesirable decrease of operation speed.
Another object of the present invention is to provide a method in which an optimum internal supply voltage is generated without undesirable decrease of operation speed.
Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
According to the present invention, a system supply voltage, supplied from an external supply circuit, is lowered to generate an internal supply voltage for an internal circuit when the system supply voltage is higher than a breakdown voltage of the internal circuit. The system supply voltage is directly supplied to the internal circuit when the system supply voltage is not higher than the breakdown voltage of the internal circuit.
According to the present invention, the integrated circuit such as an IC can be used for plural different levels of system supply voltages. When the system supply voltage VCC is lower than the breakdown voltage of the internal circuit, the system supply voltage VCC is directly supplied to the internal circuit without lowering or dropping of the system supply voltage; and therefore, it can be avoided that the operation speed of the IC is undesirably lowered.
The voltage-lowering step can be prohibited, when the system supply voltage is not higher than the breakdown voltage of the internal circuit. As a result, power consumption of a voltage lowering circuit is decreased (improved).